Video display driver with data enable learning

ABSTRACT

Data enable learning is provided for a video display driver in which a data enable signal and pixel clock exclusive of their associated horizontal and vertical synchronization signals for a digital video signal are used to facilitate generating of signals corresponding to the associated horizontal and vertical synchronization signals.

RELATED APPLICATIONS

This application claims priority from U.S. Provisional PatentApplication No. 60/932,910, filed on Jun. 1, 2007, the contents of whichare incorporated herein by reference.

BACKGROUND

Liquid Crystal Displays (LCDs) are used in a variety of products,including cell phone, digital music players, personal digitalassistants, web browsing devices, and smart phones such as the announcedApple I-phone that combines one or more of the foregoing into a single,hand-held apparatus. Other uses are in hand-held games, hand-heldcomputers, and laptop/notebook computers. These displays are availablein both gray-scale (monochrome) and color forms, and are typicallyarranged as a matrix of intersecting rows and columns. The intersectionof each row and column forms a pixel, or dot, the density, and/or colorof which can be varied in accordance with the voltage applied to thepixel in order to define the gray shades of the liquid crystal display.These various voltages produce the different shades of color on thedisplay, and are normally referred to as “shades of gray” even whenspeaking of a color display.

The image displayed on the screen may be controlled by individuallyselecting one row of the display at a time, and applying controlvoltages to each column of the selected row. The period during whicheach such row is selected may be referred to as a “row drive period.”This process is carried out for each individual row of the screen; forexample, if there are 480 rows in the array, then there are typically480 row drive periods in one display cycle. After the completion of onedisplay cycle during which each row in the array has been selected, anew display cycle begins, and the process is repeated to refresh and/orupdate the displayed image. Each pixel of the display is periodicallyrefreshed or updated many times each second, both to refresh the voltagestored at the pixel as well as to reflect any changes in the shade to bedisplayed by such pixel over time.

Liquid crystal displays used in computer screens require a relativelylarge number of such channel driver outputs. Channel drivers areconnected to a source terminal of a thin film resistor that isfabricated onto the glass of the LCD. Many smaller display devices,including cameras, cell phones and personal digital assistants, havesensors that detect the orientation of the display. Such devices maychange the view from portrait format to landscape format, depending uponthe orientation of the device. Columns, which are vertical, becomehorizontal during landscape orientation. However, the same structure(the column) is still the driven structure, even though it assumes theorientation of a row. In order to avoid confusion, this patent shallrefer to “channel driver” and that shall mean the structure for drivingthe source terminal of the thin film pass transistor.

Color displays typically require three times as many channel drivers asconventional “monochrome” LCD displays; such color displays usuallyrequire three columns per pixel, one for each of the three primarycolors to be displayed. The channel driver circuitry is typically formedupon monolithic integrated circuits. Integrated circuits serve aschannel drivers for active matrix LCD displays and generate differentoutput voltages to define the various “gray shades” on a liquid crystaldisplay. These varying analog output voltages vary the shade of thecolor that is displayed at a particular point, or pixel, on the display.The channel driver integrated circuit must drive the analog voltagesonto the columns of the display matrix in the correct timing sequence.

LCDs are able to display images because the optical transmissioncharacteristics of liquid crystal material change in accordance with themagnitude of the applied voltage. However, the application of a steadyDC voltage to a liquid crystal will, over time, permanently change anddegrade its physical properties. For this reason, it is common to driveLCDs using drive techniques which charge each liquid crystal withvoltages of alternating polarities relative to a common midpoint voltagevalue. It should be noted that, in this context, the “voltages ofalternating polarities” does not necessarily require the use of drivingvoltages that are greater than, and less than, ground potential, butsimply voltages that are above and below a predetermined median displaybias voltage. The application of alternating polarity voltages to thepixels of the display is generally known as inversion.

Accordingly, driving a pixel of liquid crystal material to a particulargray shade involves two voltage pulses of equal magnitude but oppositepolarity relative to the median display bias voltage. The drivingvoltage applied to any given pixel during its row drive period of onedisplay cycle is typically reversed in polarity during its row driveperiod on the next succeeding display cycle. The pixel responds to theRMS value of the voltage so the final “brightness” of the pixel onlydepends on the magnitude of the voltage and not the polarity. Thealternating polarity is used to prevent “polarization” of the LCmaterial due to impurities.

BRIEF DESCRIPTION OF THE DRAWINGS

Note: FIGS. 1-12 and 13-17 employ independent sets of numericdesignators for their respective elements in these drawings.Accordingly, while it may otherwise appear that some duplication occurs,all references to drawing elements should be read in context.

FIG. 1A is a block diagram showing direct video data connections from ahost processor to a matrix type of display according to one embodimentof the present invention.

FIG. 1B is a block diagram showing a serially encoded video dataconnection from the host processor to the display thorough a MobilePixel Link (MPL) interface according to another embodiment of thepresent invention.

FIG. 2 is a block diagram of a display driver according to an embodimentof the present invention.

FIG. 3 depicts operation of the LoSSI interface of FIG. 2.

FIG. 4 is a block diagram of the MPL interface of FIG. 1B.

FIG. 5 is a diagram of five configurations of RAM data according to anembodiment of the present invention.

FIG. 6 depicts operations involving the RAM of FIG. 2 according to anembodiment of the present invention.

FIG. 7 depicts operations for the DE Learning element of FIG. 2according to an embodiment of the present invention.

FIG. 8 is a timing diagram of signals involved in operations for the DElearning element of FIG. 2 according to an embodiment of the presentinvention.

FIG. 9 is a timing diagram of further signals involved in operations forthe DE learning element of FIG. 2 according to an embodiment of thepresent invention.

FIG. 10 depicts operations involving the Alpha Blend element of FIG. 2according to an embodiment of the present invention.

FIG. 11 illustrates a display with an image within a window when adisplay driver is operated in a partial mode according to an embodimentof the present invention.

FIG. 12 depicts operations for a power down mode, termination of videomode and expiration of time for displaying video according to anembodiment of the present invention.

FIG. 13 is a partial block diagram of the source driver block.

FIG. 14 is a schematic of the output channels in the source driverblock.

FIG. 15A is a schematic of the gamma generation circuit in the sourcedriver block.

FIG. 15B is one alternate embodiment of the gamma generation circuit.

FIG. 15C is another alternate embodiment of the gamma generationcircuit.

FIG. 16 shows how pixels are packed in the three-bit mode.

FIG. 17 is graphical illustration of an exemplary gamma curve.

FIG. 18 is a block diagram of a commercial embodiment of a video displaydriver system for displaying video according to an embodiment of thepresent invention.

FIGS. 19A and 19B illustrate possible negative and positive gammapolarity curves, respectively.

FIG. 20 is a table of values for gamma curves according to an embodimentof the present invention.

FIG. 21 illustrates a gamma curve adjustment according to an embodimentof the present invention.

FIG. 22 is a block diagram of a gamma reference architecture accordingto an embodiment of the present invention.

FIG. 23 is a block diagram of an AC V_(COM) circuit according to anembodiment of the present invention.

DETAILED DESCRIPTION

Various embodiments of the present invention will be described in detailwith reference to the drawings, where like reference numerals representlike parts and assemblies throughout the several views. Reference tovarious embodiments does not limit the scope of the invention, which islimited only by the scope of the claims attached hereto. Additionally,any examples set forth in this specification are not intended to belimiting and merely set forth some of the many possible embodiments forthe claimed invention.

Throughout the specification and claims, the following terms take atleast the meanings explicitly associated herein, unless the contextclearly dictates otherwise. The meanings identified below are notintended to limit the terms, but merely provide illustrative examplesfor the terms. The meaning of “a,” “an,” and “the” includes pluralreference, the meaning of “in” includes “in” and “on.” The term“connected” means a direct electrical connection between the itemsconnected, without any intermediate devices. The term “coupled” meanseither a direct electrical connection between the items connected, or anindirect connection through one or more passive or active intermediarydevices. The term “circuit” means either a single component or amultiplicity of components, either active and/or passive, that arecoupled to provide a desired function. The term “signal” means at leastone current, voltage, charge, temperature, data, or other signal.

The term “channel” identifies the circuit elements that receive digitaldata and convert the received digital data into analog voltages that areapplied to the pad locations on a glass substrate. The pads areconnected to source terminals of thin film transistors. The term “line”refers to a set of adjacent channel pixels that are connected to acommon gate signal. All the gates of adjacent thin film transistors in aline are connected to a common gate signal. One line is selected forreceiving data when its gate signal turns on the transistors in theline. In a first orientation of the display, the output channels arecolumns and the lines are rows. When the display is rotated ninetydegrees to a second orientation, the columns become rows and the linesbecome columns. The following text assumes the display is always in thefirst orientation and the terms columns and channels are interchangeableas are the terms line and row. Those skilled in the art understand thatin the second orientation, the “lines” are still the output channels andthe “columns” are selected by the gate driver.

Also, the discussion below uses a number of terms for which definitionsare provided as follow:

Normal Mode: This is the display mode in which streaming video data issent to the display. In this mode, timing is derived from the PCLK andDE signals that are received through the video interface. The PartialDisplay Memory is not used in this mode.

Partial Mode: This is the display mode in which data is read from theinternal Partial Display Memory and sent to the display. Timing to thedisplay is specified by register settings and is derived from aninternal oscillator.

Alpha Mode: This is the display mode in which image data stored in thePartial Display Memory is blended with (or overlain on) the incomingvideo data. Timing is derived from the PCLK and DE signals that arereceived through the video interface.

Partial Display Memory: On-chip memory which is used to store displaydata for the Partial Display Window.

Partial Display Window: A user-defined region on the display that isself-refreshed with image data stored in the Partial Display Memory whenthe device is operating in Partial Mode.

Color Mode: The Color Mode determines the bit depth of the data that issent to the display, and is distinguishable from Packing Mode in thatseveral different “packing schemes” could be used for a given ColorMode. For example, in Partial Mode, the BITS_PER_PIXEL register may beused to select one of the Color Modes:

-   -   1-Bit Mode: Each pixel is rendered using 1 bit (2 levels). The        same data value is used for the red, green and blue subpixels.        The source driver drive voltages can be adjusted to define a        foreground color for the data=1 condition and a background color        for the data=0 condition. The foreground and background colors        are not limited to black/white values.    -   3-Bit Mode: Each pixel is rendered using 1 bit of data (2        levels) for each of the red, green and blue subpixels. The        source driver drive voltages can be adjusted to define an        8-color palette which is not limited to the conventional B, W,        R, G, B, C, Y, M colors.    -   3-Bit Mode LP: Lower system power and reduced LoSSI write speed.        Otherwise identical to the 3-Bit Mode.    -   12-Bit Mode: Each pixel is rendered using 4 bits (16 levels) for        each of the red, green and blue subpixels.    -   18-Bit Mode: Each pixel is rendered using 6 bits (64 levels) for        each of the red, green and blue subpixels.

In Normal Mode, the output color mode is 24/18-Bit, regardless of thevalue of the BITS_PER_PIXEL register or of the PM Color Set commandstate.

Packing Mode: As data is written to the Partial Display Memory via theserial interface, it is packed according to the bit-depth that will beused when displaying the Partial Display Memory data (BITS_PER_PIXELregister). Five packing modes are provided (see FIG. 5):

-   -   1-Bit Packing: Each byte sent over the serial interface contains        six pixels.    -   3-Bit Packing: Each byte sent over the serial interface contains        two pixels.    -   3-Bit Efficient Packing: Every three bytes sent over the serial        interface contain eight pixels.    -   12-Bit Packing: Every two bytes sent over the serial interface        contain one pixel.    -   18-Bit Packing: Every three bytes sent over the serial interface        contain one pixel.        Configuration Registers: Registers which control the operating        modes and settings which effect driver behavior.

Register Access Mode: This mode allows the Serial Interface to directlyaccess the Configuration Register settings. The host CPU directlycontrols the settings of the Configuration Registers in this mode.Alternatively, the device can be controlled via the Command Mode.Register Access Mode is entered by sending the Enter Register AccessMode command.

Command Mode: This mode provides a method of controlling the displayoperation using high-level OpCodes. Each OpCode loads an associated setof Configuration Register values from an internal EEPROM. Thus, the hostCPU need not have knowledge of the Configuration Registers.Alternatively, the device can be controlled via Register Access Mode.Command Mode may be entered by sending the Enter Command Mode command orby writing any data to register address 5Fh. After a reset, the FPD95120is in the Command Mode.

Low-Speed Serial Interface (LoSSI) Protocols:

-   -   SPI Protocol: Traditional SPI-like serial interface protocol        which contains a Read/Write bit, 7-bit address field, and 8-bit        data field. If used in Command Mode transactions, the R/W-bit        plus address field is replaced by an 8-bit command and the data        field(s) is optional.    -   TSI Protocol: Serial interface protocol which contains a        Cmd/Data bit, 8-bit command (or address) field, and optional        8-bit data field(s).

With respect to the drawings, FIG. 1A is a block diagram showing directvideo data connections from a host processor 30 to a display board 32having a matrix type of display 34, such as an LCD display, and adisplay driver 36 which passes image data from the host processor 30 tothe display driver 36 according to one embodiment of the presentinvention. Two power supply voltages and ground are provided by the hostprocessor 30 to the display driver 36 on three lines of a bus 38. Videoor RGB (red, green, and blue) data is provided on 24 lines on a bus 40thus enabling the parallel transfer of up to 24 bit pixel data (8 bitsper subpixel). Also transferred are two signals on bus 42, Pclk and DE,which are synchronized by the host computer 30 to the video data. Threeor four lines on bus 44 provide a low-speed serial interface (LoSSI)between the host processor 30 and the display adapter 36, which is oneembodiment, is either encoded according to the Serial PeripheralInterface (SPI) or the Three Wire Serial Interface (TSI). A reset line46 to reset the display driver 36 by the host processor 30, and a videotransfer timing signal on line 48 from the display driver 36 to the hostprocessor 30 are also shown in FIG. 1A. The video transfer timing signaltransitions between high and low at the time that selected lines arebeing written into the display 34 in order for the host processor toupdate the partial memory RAM 82 without displaying parts of two imagesat the same time on the display 34.

FIG. 1B is a block diagram showing a serially encoded video dataconnection from the host processor 30 to the display driver 36 thorougha Mobile Pixel Link (MPL) interface circuit 50 which receives parallelvideo data from the host processor, converts it to high-speed serialdata, and places it on the 3 line MPL data bus 54 along with an MPLpower down signal on line 56 according to another embodiment of thepresent invention. The 3 line MPL data bus 54 consists of a twodifferential signal pair and a clock line. The other wires and buses,38, 44, 46, and 48, are also shown in FIG. 1B. The MPL interface circuit50 is also connected to the 3 or 4 wire low-speed serial interface 44and to the reset line 46.

FIG. 2 is a block diagram of the display driver 36 according to anembodiment of the present invention. The display driver 36 includes apower supply 70 which receives 2 power supply voltages and ground on bus38 and provides various supply voltages to the rest of the displaydriver 36 and to the display 34. Some of the voltages produced by thepower supply 70 depend on the characteristics of the display 34 andother operating conditions set by the host processor 30 shown in FIGS.1A and 1B. The display driver 36 also includes a timing and controlblock 72 which generates the timing signals used in the display driver36 and, depending on the register settings in the registers 74 and themode in which the display driver 36 is operating, provides the necessarycontrol signals to the rest of the display driver 36. The registers 74are coupled to an EEPROM 76 which holds certain nonvolatile data such asthe settings for the various registers 74 when the display driver 36 isfirst powered up and after being reset. The EEPROM 76 also holds aplurality of user set combinations of register settings so that thedisplay driver 36 can be switched to one of these stored combinations ofregister settings with a single command rather than having to directlyenter each of the desired registered settings. When the display driver36 receives a command to switch to one of the stored combinations ofregister settings, the setting stored in the EEPROM 76 are transferredto the appropriate registers 74.

The display driver 36 has a low-speed serial interface (LoSSI) 78 whichinterfaces with the data on bus 44 and processes the data as describedbelow. Except for the reset command on line 46, the display driver 36receives all of its operational commands, and sends data back to thehost processor 30 through the LoSSI interface 78. As described in moredetail below, the display driver 36 has two basic operatingconfigurations, a command mode and a register mode. When operating inthe command mode, commands received at the LoSSI interface 78 are passedto the timing and control block 72, and when operating in the registermode, register writes are made to the selected registers 74.

The LoSSI interface 78 is used to pass image data for use when thedisplay driver 36 is in the partial mode or in the alpha mode, both ofwhich are described in more detail below. The PM data packer 80 receivespartial memory data from the LoSSI interface 78, strips the data ofunused bits, and passes the remaining data to the RAM 82 as described inmore detail below. When the image stored in the RAM is to be displayed,a partial memory (PM) data formatter 84 formats the data depending onthe format of the data stored in the RAM and the operating mode of thedisplay driver 36 which is described in detail below.

The normal video data can be received by the display driver 36 as 24bits per pixel data on bus 40 together with the clock timing signal,Pclk, and the data enable signal, DE, on bus 42. Alternatively, thedisplay driver 36 can receive normal video data encoded according to theMPL standard on the three wire high-speed serial data bus 54 togetherwith an MPL link power down signal of line 56. Which mode the displaydriver 36 is set to receive the normal video data is determined by awire jumper on the display board 32 as indicated by line 86 in FIG. 2.

A video interface 90 receives the normal video data, decodes the MPLdata if the video data is sent over the MPL link, and converts the pixeldata to 24 bits per pixel if the incoming video data is 18 or 16 bitpixel data according to algorithms known by those skilled in the art.The 24 bit pixel data is then passed to a DE learning block 92 whichgenerates a substitute DE signal for the rest of the display driver 36and in so doing essentially digitally filters the DE incoming signal sothat virtually all erroneous transitions in the DE incoming signal arecorrected as described below in more detail. The DE learning block 92also detects the vertical blanking time which enables the display driver36 to operate without receiving horizontal sync or vertical sync signalsfrom the video source since the DE learning block 92 generates thesubstitute DE signal based only on the DE and Pclk signals.

The video data, after the DE learning process in block 92, ismultiplexed into sets of two pixels (2-pixel sets) processed in parallelby a video multiplexor block 94 which requires an output bus 48 bitswide. This allows the pixel data to be processed at half the data rateof the incoming video which eases the design layout requirements andlowers the power consumed by the display driver 36 since the transitionsfrom one logic state to the other can be essentially twice as long.

After the incoming data has been arranged into 2-pixel sets by the videomultiplexor 94, the 24 bit data of each pixel is converted to 18 bitdata. If the incoming video data is 24 bits per pixel, the 24 bit datacan be converted to 18 bits either by dithering or truncation of the twoleast significant bits of each color channel or subpixel (red, green,and blue) by the upscale, dithering and/or truncation block 96.

The display driver 36 has the ability to combine the video data with thedata stored in the RAM 82 in the alpha blend block 98, the details ofwhich are described in detail below. In addition to having thecapability to blend the video data and the RAM 82 data, the alpha blendblock 98 is also used when the display driver 36 is in a video upscalemode to double the size of the incoming video by mapping each incomingpixel into four output pixels.

The output from the alpha blend block 98 is coupled to a column driveror output channels 100 which, in combination with a gamma reference 102,produces the analog gray level voltages which are passed to thesubpixels in the display 34 on a bus 104 as described in detail below.Since a very common type of matrix display is an LCD type of display,the description below will describe an LCD type of display to keep fromunduly complicating the description, but it will be understood that thedisplay driver 36 can be used with other types of matrix displays.

As is well known in the industry, the LCD display 34 is a matrix ofpolysilicon transistors (not shown), which receive the analog gray levelvoltages at their sources (hence the term “source driver”) and are gatedon and off on a line-by-line basis in sequential order. These signalsare passed to the display 34 from the timing and control block 72 on abus 106. As is also well known in the industry a Vcom voltage is used toadjust the voltage level across the liquid display elements (not shown)on a dot-by-dot basis, on a line-by-line basis, or an frame-by-framebasis and are generated in the Vcom driver block 108 and passed to thedisplay 34 on a bus 110. The current polarity of the Vcom voltage ispassed to the Gamma Reference 102 to synchronize the polarity switchingof the Vcom voltage and the Gamma Reference voltage. The power supplyvoltages required by the display 34 and are passed to the display 34 ona bus 112.

Low Speed Serial Interface Protocols in Display Driver 36 and MPLEncoder 50

In general terms the display driver 36 is controlled by the contents ofthe registers 74, although the display driver 36 can be controlled bytransactions sent over the low speed serial connection 44 which aredecoded by the LoSSI interface 78 as either direct commands or as writesto the registers 74. Depending on the state of the registers 74, or inresponse to a direct command, the display driver 36 either storespartial mode data in the RAM 82, enters into one of several modes ofoperation or performs other miscellaneous actions such as providingstatus data back to the host processor over the low speed serialconnection 44.

Turning now to FIG. 3, the flow of data into the LoSSI interface block78 is shown in the flow diagram 120. As shown in FIG. 3 the LoSSIinterface block 78 monitors the incoming serial data in step 122 (“Isdata being received on the low speed serial interface with the chipselect enabled?”). If the serial data bus is 3 wires (without a chipselect line), the serial data is always decoded in step 124 (“Serialdata decoder”). If the serial data connection is 4 wires (with a chipselect line), the LoSSI interface block passes the serial data to theserial decoder step 124 only if the chip select line is enabled to thedisplay driver 36 when the serial data is received by the LoSSIinterface block 78.

The display driver 36 can receive serial data according to one of twodifferent protocols, the serial peripheral interface (SPI) and theThree-Wire Serial Interface (TSI) which is essentially the same protocolas the SPI protocol but with an additional synchronization bit at thebeginning of a single read or write, and with an additional “1” bitbetween successive 8 bit data blocks in a multiple write operation.

The LoSSI interface can be used in a system in which the display driver36 receives serial data which may be sent also to another peripheraldevice using the same serial bus 44 which has the chip select signal. Inthis mode of operation, the display driver 36 has a LoSSIlocked/unlocked register which holds data that disables (locks) theLoSSI interface 78 or enables (unlocks) the LoSSI interface 78. The hostprocessor 30, if it is to send serial data to the display driver 36switches the LoSSI interface from locked to unlocked, if necessary, bysending a predetermined register write command to the LoSSIlocked/unlocked register in the register block 74. Conversely, if thehost processor wants to send serial data to another peripheral devicewhich shares the serial bus 44, the host processor must lock the LoSSIinterface 78, if necessary, before communicating with the otherperipheral device.

As shown in FIG. 1B, the MPL encoder 50 shares the same serial bus 44with the display driver 36. FIG. 4 is a block diagram of the MPL encoder50 which includes MPL encoder circuitry 130 that receives the 24 RGBlines on a bus 132, the Pclk and DE enable on a bus 134, the MPL powerdown signal on line 136, various other control and timing signals forcontrolling the MPL encoder 50 are on a bus 138, and power and groundare on a bus 140. As shown in FIG. 1B the MPL encoder 50 is connected tothe display driver 36 by a three wire bus 54 and the MPL power down line56 which couple signals to and from the display driver 36 by a pluralityof line drivers and receivers 142. The MPL encoder 50 also includes anencoder configuration serial interface 144 which is connected to thethree or four line low speed serial bus 44. The fourth line 146 is shownas a dashed line indicating that it is an optional line. With the fourthline 146 separate data in and data out lines are available rather thanusing a single data line for bidirectional data flow. The encoderconfiguration serial interface 144 is coupled to registers 148 which areused by the MPL encoder circuitry 130 to select the parameters of theoperation of the MPL encoder 50.

Since the signals between the host processor 30 and the display driver36 must pass through a hinged connection in a flip phone, it isdesirable to keep the number of separate conductors to a minimum. Theuse of MPL encoder data and a three wire low speed serial interfacehelps to reduce the number of separate conductors to a minimum.

The encoder configuration interface 144, like the LoSSI interface 78, isin either a locked state meaning that all serial data is ignored excepta command to write an unlock code to the registers 148, or in theunlocked state in which all incoming serial data is decoded if the chipselect line 146, if present, is enabled, and is always decoded andprocessed if there is no chip select line 146. For simplicity, the lockand unlock control register for the display driver 36 and the MPLencoder 50 have the same address, and the lock/unlock code is the datain the registers enabling the host processor to write a firstlock/unlock code which will unlock one of the display driver 36 or theMPL encoder 50 and also lock the other serial interface, or can send anlock/unlock code which will lock both serial interfaces in oneembodiment of the invention. After the reset line 46 is activated, thedisplay driver 36 will be in the unlocked state and the MPL encoder 50will be in the locked state in one embodiment of the invention. Thus,when the display driver 36 is used without an MPL connection, the LoSSIinterface 78 will be unlocked and ready to process serial data on thelow speed serial data bus 44, and the host processor 30 will not have towrite unlock data to the lock/unlock register.

Returning to FIG. 3 step 160 (“Is LoSSI block locked?”) determines ifthe LoSSI interface 78 is locked or not, and if it is, the data isexamined in step 162 (“Is data an unlock register write?”) to see if itis an unlock code. If the data is not an unlock code, the LoSSIinterface 78 ignores the serial data and waits for the next segment ofserial data. If the data is an unlock code, the appropriate data iswritten into the lock/unlock register to unlock the LoSSI interface 78in step 164 (“Unlock LoSSI block”), and the serial interface 78 waitsfor the next segment of serial data.

If the LoSSI interface is unlocked, the serial data is examined todetermine if it is a write to the RAM 82 in step 166 (“Is serial dataRAM data?”). If the serial data is not a write command to the RAM 82,the data is processed as a command or a register write depending onwhether the display driver 36 is in the command mode or the registermode. Step 168 (“Is the display driver in command mode?”) determineswhich of the two modes the display driver 36 is in, and if it is theregister mode, the data is written to the addressed register asindicated in block 170 (“Place the serial data into the addressedregister”). The addressed register may be the register that stores thecommand mode or register mode configuration data to the display driver36, in which case, assuming that the serial data configures the displaydriver 36 into the command mode, the display driver 36 would switch tothe command mode, and the LoSSI interface 78 would await the nextsegment of serial data. If the display driver 36 is in the command mode,the command is executed in step 172 (“Execute the command”). Similar tothe register write which switches the display driver 36 to the commandmode, the command being executed in block 172 may be a command to switchthe display driver 36 to the register mode.

Partial Memory Image Data Transfer into the RAM 82

If the serial data into the LoSSI Interface 78 is to be written into theRAM 82, the data is transferred to the PM Data Packer where the serialdata is parsed and sent to the RAM 82 depending on the format of the RAMdata in the serial data in step 174 (“Parse the input data according tothe format of the LoSSI data and store the parsed data in the RAM”) inFIG. 3. FIG. 5 is a diagram of the five different configurations of theRAM data in each word of the serial data. In FIG. 5 the left hand bit isthe first serial bit to arrive at the LoSSI Interface 78. The fiveconfigurations are a 1-bit per pixel configuration 180, a 3-bit perpixel standard configuration 182, a 3-bit per pixel efficient packingconfiguration 184, a 12-bit per pixel configuration 186, and an 18-bitper pixel configuration 188. When the RAM 82 is to be filled with 1-bitper pixel data shown in configuration 180, the first two bits areignored, and the next six bits are data for six pixels. When the RAM 82is to be loaded with 3-bits per pixel data, the pixel data can be sentto the display driver 36 in one of two configurations, the configuration182 in which each serial data word holds data for two pixels, and theefficient packing configuration 184 in which three serial data wordsprovide pixel data for eight pixels. Thus, the efficient packingconfiguration provides faster transfer of 3-bit per pixel data into theRAM 82 than configuration 182 by a factor of 8 to 6 in each of threeserial data words. This faster transfer of data enables the partialmemory image to be updated faster, which may allow the partial memoryimage to be perceived as more animated than if the configuration 182were used to place 3-bit pixels into the RAM 82. The 12-bit per pixelconfiguration 186 uses two serial words to load the 12-bit pixels intothe RAM 82, and the 18-bit per pixel configuration 188 uses three serialwords to load the 18-bit pixels into the RAM 82.

Read Rate From the RAM 82

FIG. 6 is a flow diagram 200 of the transfer of partial memory data fromthe RAM 82 to the output channels 100 and the transfer of video ornormal RGB data from the video input lines 40, 42, 54, and 56 to theoutput channels 100. The flow of pixel data from the RAM 82 to theoutput channels 100 is on the left side of FIG. 6 which begins by adetermination if the display driver 36 is in either the partial mode,meaning that the image in the RAM 82 is to be displayed, or the alphamode meaning that the image in the RAM 82 is to be combined with thenormal video data as indicated in step 202 (“Is the display driver inpartial mode or alpha mode?”). If the display driver 36 is in thepartial mode or the alpha mode, the partial image data is read from theRAM 82 at a constant rate that depends on the partial modeconfigurations as indicated in step 204 (“Read data from the RAM at arate determined by the format of the data stored in the RAM and whetherthe display driver is in normal power or low power”). The partial modeconfigurations include whether the display driver 36 is in alpha mode inwhich case the timing of the reading of data from the RAM 82 is set bythe Pclk, or not in alpha mode in which case the timing of the displaydriver 36 is set by an internal oscillator which may have a frequency ofapproximately 13.0 MHz. Other partial mode configurations which affectthe RAM read rate is whether the partial mode operation is at normalpower or low power, and whether the image is to be upscaled for a 2×increase in the size of the image. These other partial modeconfigurations are described in more detail below.

Low Power Partial Mode

In the flow diagram of FIG. 6 a determination is made in step 206 (“Inlow power mode?”) whether the partial mode is in the normal power modeor the partial mode. If in normal power mode, the RAM 82 data isformatted into 18-bit pixels by placing zeros in the least significantbit positions if necessary in step 208 (“If necessary, format the datainto sets of two 18 bit pixels to form 2-pixel groups”). If in low powermode, which may be selected by the host processor 30 only if the data inthe RAM 82 is 1-bit per pixel or 3-bits per pixel, each 18-bits of datasent to the output channels 100 will have data for 4 pixels allowing thepartial mode oscillator clock (not shown) to be divided by 4 thusreducing the power consumed by the display driver 36 to be essentiallyone-fourth of the normal power. When the display driver 36 is in lowpower mode, two sets of 18-bit pixels are transferred to the outputchannels 100 at a time, data for 8 pixels is transferred to four latchesof the output channels 100 at a time as indicated in step 210 (“Setaddress lines to the first line latch so that four 2-pixel groups areload at a time using the same 36 bits”) where the term “First Row ofLatchs” refers to the row of latches 110 shown and described in theAttachment B to this application.

Partial Upscale Mode

As shown in FIG. 6, if the partial mode is in normal power mode thepartial memory RAM 82 data can be upscaled in step 212 (“Upscale PMdata?”). Since in upscale mode each pixel is replicated in an adjacentcolumn and in an adjacent line, the loading of data into the columnlatches is modified so that the sets of two-pixel data, or 36 pixelbits, consist of the data for one pixel replicated to fill both pixelpositions as indicated in step 214 (“Load the first line latch so thatboth pixels have the same data value”). In addition, in order to providetwo adjacent lines of the display with the same pixel data, the firstline latch is loaded after every other line of the display is written instep 216 (“Load the first line latch once for every 2 lines output”).Whether the partial mode is in the low power mode or the upscale mode,the resulting partial data is passed to an alpha blend block 218 (“Alphablend”) which may or may not blend the normal power partial data withthe normal video data and the resulting data is passed to source drives100 as indicated in step 220 (“Send pixel data to the source drivers”).After the 2 pixel data has been written to the output channels 100, thedisplay driver 36 begins the cycle again depending on whether thedisplay driver 36 is in the partial mode or the normal mode asdetermined in step 222 (“In partial mode?”) of FIG. 6.

Normal Video Mode

In the normal video mode the data is input to the display driver 36 asRGB 24 bit video or MPL video in steps 230 (“Is the display driver inRGB video mode?”) and 232 (“Is the display driver in MPL mode?”),respectively. If the normal video data received is RGB 24 bit data, thedata is sent directly to the video interface 90 where it is formattedinto 24 bit pixels if necessary, the DE pulse is delayed, and thetransitions in the DE pulse are synchronized with the Pclk in step 234(“Transform all non-24 bit input data to 24 bits/pixel, delay andsynchronize DE”). If the normal video data received is MPL data, it isdecoded to parallel data in step 236 (“Decode MPL data”). After thenormal video data is normalized by the processes in step 234, the normalvideo data is passed to DE Learning 92 and digitally filtered asindicated in step 238 (“Remove extraneous transitions in the DE input”).The operation of the DE Learning block is described in the DE Learningsection below.

After the normal video data has passed through the DE Learning block 92,two normal video pixels are arranged as 36 bits of parallel data in theVideo Mutiplexing block 94 in FIG. 2 in step 240 (“Double bus width toform a group of 2 pixels”) in FIG. 6. The resulting video data is passedto the Upscale, Dithering and/or Truncation block 96 in which thedetermination is made if the video data is to be upscaled in step 242(“Upscale video data?”). If the normal video is not to be upscaled, thePclk frequency is divided by 2 for use in the rest of the normal modeprocessing in step 244 (“Expand PCLK period by 2 for use in the rest ofthe normal mode operations”). If the normal video data is to beupscaled, then each 24 bit pixel is replicated so that each of the twosets of pixels being processed in parallel are the same in step 246(“Set address lines to the first line latch so that two 2-pixel groupsare loaded at a time using the same 36 bits”). Then the line timing isadjusted such that two output lines are written for each one line ofvideo in step 248 (“Set the display line timing such that 2 output linesare written each 1 input video line”).

The determination is made as to whether the 24 bits per pixel are to bedithered to 18 bits per pixel or if the last two bits of each subpixelare to be truncated in step 250 (“Is dither mode enabled?”). Ditheringof the 24 bit data, if applicable, is performed in step 252 (“Dither 24bit data to 18 bit data”), otherwise the 24 bit data is truncated instep 254 (“Truncate last 2 bits of each subpixel”). The resulting18-bits per pixel data is then passed to the alpha blend block 98 inFIG. 2 in step 218.

DE Learning

In the DE Learning block 92 the number of Pclk periods that the DEsignal is low is counted during each DE pulse, and if two successivecounts are the same, the count is labeled the Learned DE Low count. Thiscount does not change until there are two subsequent successive DE lowcounts which are the same but different than the previous Learned DE Lowcount. The same principal is applied to the DE period, that is, thenumber of Pclk periods between successive falling edges of the DE signalare counted, and if two successive DE period counts are the same, thecount becomes the Learned DE Period count. By generating the Learned DELow count and the Learned DE Period count a one time variation in the DElow time or the DE period will not change the learned DE low count orthe learned DE period count, respectively. The DE pulses are not presentduring the vertical blanking period of the display, and by detecting theabsence of the DE pulses at the beginning of the vertical blankingperiod and the total time when the DE pulses are present and absentuntil they reappear, the number of valid lines and the number of totallines can be learned.

FIG. 7 is a flow chart 240 of the DE learning process between the circleA and circle B in FIG. 7 to provide a digitally filtered DE signal. Asshown in FIG. 8 the Learned DE Low count and the Learned DE Period countbegin when the first DE pulses are input to the DE Learning block 92 inFIG. 2, while the learning of the Learned Valid Lines and the LearnedTotal Lines only begins after the Learned DE Low count and the LearnedDE Period count are nonzero. In FIG. 7 the number of Pclk periods duringthe low pulse of the DE signal is counted twice in steps 242 (“Countpclk periods in a DE low pulse beginning one pclk period after DE fallsand ending one pclk period after DE rises”) and 244 (“Count pclk periodsin the next DE low pulse beginning one pclk period after DE falls andending one pclk period after DE rises”), respectively, and the twocounts are compared in step 246 (“Are the two counts the same?”). If thetwo counts are the same the Learned DE Low count is set to the lastcount in step 248 (“Set the DE learned low count to the last count”). Ifthe two counts are different, then an additional count is made in step244 and compared to the last count. This process continues until twosuccessive counts are the same and the Learned DE Low count is set.After the count is set, during the next DE pulse the number of Pclkperiods during the low state of the DE pulse is counted in step 250(“Count pclk periods in the next DE low pulse beginning one pclk periodafter DE falls and ending one pclk period after DE rises”), and if thelast two counts are the same, the last Learned DE Low count is set tothe last count in step 252 (“Are the last two counts the same?”). If thetwo counts are not the same, the number of Pclk periods during the lowstate of the next DE signal is counted as indicated in block 250 andthen compared to the last count in step 252. Thus the Learned DE Lowcount does not change unless there are two successive counts that arethe same but different than the current Learned DE Low count. Thisprocess not only digitally filters the DE low pulse time, but alsoallows the display driver 36 to adjust to a new DE signal with adifferent low pulse time. Conversely, if there should be two glitchesthe same during two successive DE low pulse times, the Learned DE Lowcount will erroneously change, but will be corrected when two glitchfree DE low pulses occur in a row. Since the display driver 36 in oneembodiment refreshes the display sixty times a second, the one timeglitch will result in virtually no perceptible change in the displayedimage.

In the same manner as the Learned DE Low count is calculated, theLearned DE Period count is calculated. Thus the processes in steps 254(“Count pclk periods in a DE period beginning one pclk period after DEfalls and ending one pclk period after DE falls again”), 256 (“Countpclk periods in the next DE period beginning one pclk period after DEfalls and ending once pclk period after DE falls again”), 258 (“Are thetwo counts the same?”), 260 (“Set the DE learned period count to thelast count”) and 262 (“Are the last two counts the same?”) are the DEperiod counterparts of the processes in steps 242, 244, 246, 248, and252, respectively. The process set forth in step 264 (“Count Pclkperiods in the next DE period beginning one Pclk period after DE fallsand ending one pclk period after DE falls again and provide a learned Xcount number which is a running count of the pclk periods during thecount”) performs the DE period counterpart of the process in step 250,but in addition generates a running count of the Pclk periods during theperiod count. This running count is used to determine when a DE pulse ismissing indicating the start of the vertical blanking period.

FIG. 8 is a timing diagram of the relevant signals used to determine theLearned DE Low count, the Learned DE Period count, the Learned ValidLines count, and the Learned Total Lines count. Shown at the top of FIG.8 is the Pclk which in this embodiment is symmetric. Below the Pclk is areset signal labeled reset_n from line 46 in FIG. 1A. Below the resetsignal is the DE signal on bus 42 which has been delayed by two DEsignal periods as indicated by the label de_d2. The relative lengths ofthe low pulses and the high pulses of the DE signal have been distortedin FIG. 8 to better illustrate the invention. Typically the width of thelow pulse, which is the horizontal blanking period, is less than 5% ofthe width of the high pulse. The falling edge of de_d2 is used togenerate a falling edge signal de_fe which begins on the falling edge ofde_d2 and is one Pclk period wide. Similarly, the rising edge of de_d2is used to generate a rising edge signal de_re which begins on therising edge of de_d2 and is also one Pclk period wide. Below the de_repulse signal is a counter labeled de_cnt which begins after the nextfalling edge of de_fe after the reset is deactivated by going high, andthe count increments for each Pclk period until the next falling edge ofde_fe, at which point it resets to a “1” count to begin the count again.

In a line labeled last_de_low is the number of Pclk periods counted fromthe falling edge of de_fe to the next falling edge of de_re beginningafter the display driver 36 comes out of reset. As shown in FIG. 7 thefirst count of the last_de_low is 2, and the same is true for the nextDE low pulse. As a result the learned_de_low changes from 0 to 2 afterthe second last_de_low count. Similarly, the last_de_per begins countingat the first falling edge of de_fe after the display driver 36 comes outof reset, and stops counting at the next falling edge of de_fe, at whichpoint the last_de_per count starts again. After two consecutive countswhich are the same, the learned_de_per is set to the last count of theof the last_de_per. After the Learned DE Low count is other than 0, andthe Learned DE Period count is other than 0, the learned_x_cnt counterbegins counting at the next falling edge of de_fe and starts recountingon the next falling edge of de_fe after the learned_de_cnt reaches thesame count as the Learned DE Period count.

Shown in FIG. 8 are three errors in the DE signal at reference numbers270, 272, and 274. The dashed lines show what the correct DE signalshould be. Each of these errors changes the de_cnt, the DE Low count,and the DE Period count as shown in FIG. 8. But because none of theseerrors produces two consecutive erroneous de_cnt with the same count,two consecutive erroneous DE Low counts with the same count, or twoconsecutive erroneous DE Period counts with the same count, thelearned_x_cnt, the Learned DE Low count, and the Learned DE Periodcounts are unchanged, and these three errors are filtered out of thegenerated DE signal used by the rest of the display driver 36.

FIG. 9 is a timing diagram of a whole frame and is shown lasting for 8DE periods to facilitate the illustration of the present invention. Inpractice, since each DE period corresponds to one row written into thedisplay 34, the number of DE periods in each frame is much higher,usually in the hundreds. The DE pulses 276 shown as dashed linesindicate the vertical blanking period in each frame.

Returning to FIG. 7 and with reference to FIG. 9, a step 280 (“Are thelearned DE low pulse count and the learned DE period count both>0?”)shows that the process to determine the Learned Valid Lines and theLearned Total Lines does not begin until the Learned DE low count andthe Learned DE Period count are both nonzero. The Learned DE Low countand the Learned DE Period count are set to zero when the display driver36 is reset. After that condition is satisfied the number of verticalblanking lines are counted in steps 282 (“Count the number of verticalblanking lines”) and 284 (“Is DE high for 2 pclks in the next DEperiod?”) which also finds the first valid line. The line counter is setto 1 in step 286 (“Set the line counter to 1”), and a test is made insteps 288 (“Is DE high for 2 pclks in the next DE period?”) and 290(“Increment the line counter”) to find the first DE period of thevertical blanking. Then step 292 (“Have the valid lines been countedtwice”) determines if the present line count is the first valid linecount. If not, the Learned Valid Line count is set to the current linecount in step 294 (“Set learned valid lines to vast valid line count”),and in step 296 (“Set learned total lines to learned valid line countplus the number vertical blanking lines”) the Learned Total Line countis set to the current line count plus the number of vertical blankinglines determined in steps 282 and 284. Then the first line is found insteps 298 (“Increment the counter”) and 300 (“Is DE high for 2 pclks inthe next DE period?”). Step 302 (“Have the total lines been countedtwice?”) determines if the total lines have been counted twice, and ifnot, the operation moves to step 286. If the total lines have beencounted twice, the two counts are compared to determine if they are thesame in step 304 (“Are the last 2 total line counts the same?”), and ifnot the operation moves again to step 286. If the two counts are thesame, the Learned Total Lines count is set to the last line count instep 306 (“Set learned total lines to last total line count”) and theoperation returns to step 286. If the test in step 292 determines thatthe valid lines have been counted twice, the two counts are compared todetermine if they are the same in step 308 (“Are the last 2 valid linecounts the same?”), and if not the operation moves again to step 298. Ifthe two counts are the same, the Learned Valid Lines count is set to thelast line count in step 310 (“Set learned valid liens to last valid linecount”) and the operation returns to step 286. The no operation (NOOP)steps 312, 314, and 316 are flow diagram tools used to correctly showthe processing flow of the DE Learning procedure.

If the Learned DE Low count or the Learned DE Period count changesduring the DE learning process, which operates continuously unless thedisplay driver 36 is in a reset state or a sleep state, then the DElearning process is restarted.

Alpha Blending

FIG. 10 is a process flow diagram 320 showing the operation of the alphablend block 98 in FIG. 2. As shown in FIG. 10 partial mode data atcircle C is passed to the output at circle E of the alpha blend block 98if the display driver 36 is in the low power mode in step 322 (“In lowpower mode?”) since the low power mode is not compatible with blendingRAM 82 data and normal video data. Next a determination is made if thedisplay driver 36 is in the alpha blend mode in step 324 (“In alphablend mode?”), and if not, the partial mode data is passed to the outputat circle E. Next a determination is made if the normal 2-pixel set isoutside the defined partial window in step 326 (“Is the normal video2-pixel set outside the defined partial window?”). If so, the partialmode data is held until a normal 2-pixel set that is inside the definedpartial window is presently being processed, the defined partial windowbeing defined by the partial memory starting and ending rows and thepartial memory starting and ending columns which are set in registersthat the host processor 30 can change to place the partial memory windowat a desired location on the display 34. If the normal pixel data beingdisplayed is at least partially in the defined partial window, eachpixel of the two-pixel set is then processed separately and in paralleland later recombined before being passed to the output channels 100through the output circle E of the Alpha Blend block 98.

Normal video data, if present, enters the alpha blend flow diagram 320at circle D and the determination is made in step 328 (“In alpha blendmode?”) if the display driver 36 is in alpha mode. If not the normalvideo data is passed directly to the output at circle E. If the displaydriver 36 is in the alpha blend mode a determination is made in step 340(“Is the normal video 2-pixel set outside the defined partial window?”)if the normal video 2-pixel set is outside the defined partial window.If so, the normal video 2-pixel set is passed to the output at circle E.

Each of the two pixels in the 2-pixel set is blended separately and atthe same time and in the same manner. The partial memory pixel isexamined in step 342 (“Is the display driver in the transparent mode andthe 1st pixel of the PM 2-pixel set=0?”) to determine if the displaydriver 36 is in the transparent mode, and if so, if the partial memorypixel data is all zeros (i.e., each of the three subpixel data is allzeros). If both conditions are satisfied, the partial memory pixel isignored in step 344 (“Ignore the first PM pixel”). If one of theseconditions is not satisfied the individual subpixels of the partialmemory pixel are scaled down, if necessary, in step 346 (“Arithmeticallydivide subpixel data of the 1st pixel of the 2-pixel set according toblend level”) to 75%, 50%, 25%, or 0% (set to all zeros) of theirnumerical value by methods well known in the art. In the normal videocounterpart of this process, the partial memory pixel is also examinedin step 348 (“Is the display diver in the transparent mode and the 1stpixel of the PM 2-pixel set=0?”) to determine if the display driver 36is in the transparent mode, and if so, if the partial memory pixel datais all zeros (i.e., each of the three subpixel data is all zeros). Ifboth conditions are satisfied, the normal video first pixel is placed inthe first pixel position of the modified 2-pixel set to be formed instep 350 (“Place the first video pixel in the first pixel position ofthe reconstructed 2-pixel group”). If one of these conditions is notsatisfied the individual subpixels of the normal video pixel are scaleddown, if necessary, in step 352 (“Arithmetically divide subpixel data ofthe 1st pixel of the 2-pixel set according to blend level”) to 0%, 25%,50%, or 75% of their numerical value and the scaled partial memorysubpixels and the scaled normal video subpixels are added together instep 354 (“Arithmetically add together the subpixel data”). The blendedpixel is placed in the first pixel position of the modified 2-pixel setto be formed in step 356 (“Place the first blended pixel in the firstpixel position of the reconstructed 2-pixel group”).

The second pixel of the incoming 2-pixel set of the partial memory dataand the normal video data is processed in the same manner as the firstpixel of the 2-pixel set in steps 362 (“Is the display driver in thetransparent mode and the 2nd pixel of the PM 2-pixel set=0?”), 364(“Ignore the second PM pixel”), 366 (“Arithmetically divide subpixeldata of the 1st pixel of the 2-pixel set according to blend level”), 368(“Is the display driver in the transparent mode and the 2nd pixel of thePM 2-pizel set=0?”), 370 (“Place the second video pixel in the secondpixel position of the reconstructed 2-pixel group”), 372(“Arithmetically divide subpixel data of the 1st pixel of the 2-pixelset according to blend level”), 374 (“Arithmetically add together thesubpixel data”), and 376 (“Place the second blended pixel in the secondpixel position of the reconstructed 2-pixel group”) which correspondwith steps 342, 344, 346, 348, 350, 352, 354, and 356, respectively.

Controlling the Position of the Image on the Display

Turning to FIG. 11, there is shown a display 600 carrying a DisplayImage (DI) 602 in window 604 which may be a normal video image or animage generated when the display driver 36 is in partial mode. The DI602 is defined by a set of coordinates on the display. Those coordinatesare the starting column 606, the ending column 608, the starting row 610and the ending row 612. The balance of the display 600 surrounding theDI 602 is the border 614. DI 602, for example, may include a backgroundcolor region 616 that surrounds a trademark or logo region 618associated with the device itself, or with the service provided by thedevice. The image 602 is displayed automatically when the device entersits partial mode of operation. The device may enter low power after apreset time without any user input. Transition to the low power mode andthe reduced display may also be limited to battery charge status.

The RAM 82 described above is used to store image data for local refreshof the display. It may be used as the sole video source in partial modeor its contents can be blended with (or overlaid on) the incoming videodata in alpha blend mode. While operating in partial mode, system poweris greatly reduced because the video controller in the system may beshut down. In this mode, image data is read from the RAM 82 and used torefresh the display. All display refresh timing is derived from theinternal oscillator (not shown) so that no external video signals arerequired.

In the preferred embodiment, the RAM 82 contains 230,400 bits of memory.This size is sufficient to display an 80×320 window of 3-bit data, orany equivalent size in terms of the totals pixels contained in thedisplay window (DW) multiplied by the color depth of each pixel.

The system processor senses when the device enters a power down mode,termination of the video mode and/or when the time for displaying videomode expires. Instructions stored in a memory may then operate thedisplay to load the display with data from the RAM 82. The steps forcarrying out this operation are shown on FIG. 12.

As a first step 620 (“Place border pixels in the SD top row oflatches”), the display driver 36 reads the border data into the display.Border data may be stored in all of the first row of latches identifiedwith reference numeral 110 in the Attachment B to this applicationinasmuch as it is the same for all border pixels.

In the next step 622 (“Is the next line to be sent to the glass lessthan the partial display window starting line or greater than thespecified partial display window ending line?”), the display driver 36reads the RAM 82 and the data in the registers 72 for the DI 602. Asexplained elsewhere in this patent, the output of the RAM 82 is suppliedto the output channels 100 via a pair of buses. The addresses of thedata are examined and if the pixel is outside the coordinates of the DI,the pixel is a border pixel and remains unchanged, the answer is “yes”and the pixel in the latch remains the same and the pixels in the latchare sent to the display 34 in step 624 (“Display the pixels encoded inthe SD first line latch”). However, if the pixel is in the DW, thedisplay driver 36 proceeds to the next step, 626 (“Place the next lineof the image in the SD top row of the latches starting at the latchcorresponding to the partial display window starting column and endingat the latch corresponding to the partial display window endingcolumn”).

In that step, the non-border pixels are loaded into the top latch,multiple columns at a time, to form a row of the DW. As explainedelsewhere, the display driver 36 provides efficient data packing so thatmultiple columns are filled at the same time. The output channels 100receive 36 bits of data at a time, and due to data packing, as many aseight columns may be filled in one clock cycle. Thereafter, the sourcedriver loads the output channels as described above until an entire lineof pixels is in the first row of latches identified with referencenumeral 110 in the Attachment B to this application. Upon completion ofloading, the pixels are displayed as provided in step 628 (“Display thepixels encoded in the SD firs line latch”).

If the last line displayed was the DW ending row 612, the display driver36 repeats the steps described above. See step 630 (“Was the last linedisplayed the partial display window ending line?”). If not, theprocessor checks to see if the display has gone into vertical blanking(step 632: “Has the display gone into vertical blanking?”). If so, theprocessor jumps to step 622 and repeats the subsequent steps.

The host processor 30 is thus able to position the image on the display34 by loading the appropriate registers 78 with the display windowstarting line, the display window ending line, the display windowstarting column, and the display window ending column. By this methodthe image can be moved up or down with two register writes to load newstarting and ending line numbers, can be moved right or left with tworegister writes to load new starting and ending line numbers, or can bemoved to a new vertical and horizontal position with four registerwrites to the display driver 36. Thus the image can easily be positionedto operate as a screen saver.

Gamma Compensation

Turning to FIG. 13, a Source Driver Circuit (SDC) 100 provides digitalimage data to output channels 200 coupled to the sources of the passtransistors. Gamma generator circuit (GGC) block 300 converts inputdigital image data to analog voltages required to drive the source lineson the glass. The digital image data may come from a streaming videointerface or another source such as a register, a full frame memory, ora partial display memory. The SDC has a predetermined number of outputchannels 200. In the preferred embodiments, there are 320 outputchannels. Each output channel receives RGB data for one pixel andperforms a digital-to-analog conversion of the red, green, and blue datain a time-multiplexed sequence that is synchronized to the glassdemultiplexor select signals (CKH1-3). The conversion sequence of theRGB data within each line time is determined by the settings for a firstregister.

A register bit in the first register controls the data loading directionof the output channels. For display applications in which thepixels/line of the glass is less than 320 channels, a second registercan be used to specify which outputs are active and which outputs areunused by the application. This can help optimize the source linefan-out region between the driver and the glass active region. Thesecond register is specified in conjunction with the first registersetting. If the load direction is set for the S0→S319 direction, thesecond register is referenced to the S0 output. If the load direction isset for the S319→S0 direction, then the second register is referencedwith respect to the S319 output.

The voltage transfer characteristic of the channel driver DAC isdetermined by the 64 gamma reference voltages generated by the GammaReference Circuit (GGC). The drive strength for the channel driveroutput is also programmable to optimize settling and power performancefor panels of various sizes and parasitic capacitive loads.

There are four different intrinsic gamma curves available in thepreferred embodiment of the gamma generation block 300. It generates 64reference voltages for each gamma curve. The intrinsic curves mayaccomplish various goals for the module user. One goal might be toobtain matching optical performance from various module suppliers. It iseven possible to optimize the individual curve shapes for the differentcolor channels of a given supplier. In these cases, the four curveoptions can be optimized for each of the module supplier's glasscharacteristics and the selection of the proper curve and settings ispossible.

Another reason for using multiple intrinsic curve settings might be toprovide multiple gamma characteristics (e.g. γ=1.0, 1.8, 2.2, 2.5) for agiven module in order to optimize performance for various viewingconditions and applications. In this case, the various curves can beselected via a Gamma Set command or through direct register access tothe Gamma Register settings.

After selecting the intrinsic curve that most closely matches thedesired characteristic, the curve shape can then be further optimized asexplained later in this patent. Four shapes are used in the preferredembodiment, but those skilled in the art understand that the inventionmay be practiced with one or any number of gamma selection curve shapes.The user may select one shape for all colors or choose separate curvesor adjustment settings for each color channel. This same intrinsic shapemay be used for the green and blue curves with different optimizationsettings, or different intrinsic shapes and optimization settings may bechosen for each color channel. For a given color channel, the sameintrinsic curve shape may be used for both drive polarities. Othercustomized gamma curves may be generated from the disclosedgamma-generating block, for example, by adding output multiplexors withmore than 4-to-1 selections.

Source Driver Circuit: Output Channel Block

The Source Driver Circuit (SDC) 100 has two major circuit blocks. One isthe output channel block 200 that carries the digital image data foreach pixel. Each column is a channel. The other is the gamma generatorcircuit block 300.

The SDC 100 operates in two modes: a normal mode where video datastreams into the LCD and a low power mode (three-bit or one-bit) wheredata from the partial RAM or other memory drives the display. Turning toFIG. 14, the SDC 100, in the normal mode, loads each channel 400.n in arow, two channels (columns) at a time. Data is carried over even and oddbusses 202, 204. A eight-bit address bus 205 runs to address decoders208.n. There is one decoder 208 for each pair of even and odd channels.After the first latch row 110 is fully loaded, its data are transferredto a second latch row 120. Each channel (column) 400.n has a decoder 60that converts an input digital data signal to an output analog voltagefor driving a sub-pixel. The analog voltage is applied to a column pad20 n. The glass demultiplexors 30 RGB and pass transistors 40 at theintersections of rows and columns switch the analog voltage on the pads20 n to the liquid crystal sub-pixel in the display.

In normal mode, video data streams to the SDC 100 from the systemprocessor. The image data is loaded into the output channels 400 andeach data value is converted into analog voltages supplied from thegamma generation block 300 to drive the color pixels in a liquid crystaldisplay. Normal mode uses eighteen (18) bits of data for each pixel.Each pixel has three sub-pixels, one for red, a second for blue andthird for green. Each sub-pixel is a 6-bit word. Thus, there are 18 bitsof data for each pixel including three 6-bit words, one for eachsub-pixel. The output channels 200 convert the digital data value foreach sub-pixel into an analog voltage for driving the sub-pixel.Conversion is done one color at a time and each color conversion may bemade with a separate gamma for each color. The driving analog voltage isapplied to the liquid crystal at the sub-pixel location in the display.The magnitude of the applied driving analog voltage controls thetransmissivity of the liquid crystal in a manner well known to thoseskilled in the art.

Source Driver Circuit: First and Second Latches

As shown in FIG. 14, the SDC 100 outputs 36 bits of data at a time tothe output channels 200. The data are fed over two busses 202, 204. Inthe normal mode, each bus carries 18 bits of data for one pixel andtogether the busses 202, 204 carry the data for two adjacent (even andodd) columns. The pixel address block 208 directs the data from one busto the even latches in row 110 and the data for the other column to theodd latches in row 110. There is a latch for each pixel. Within eachlatch are three six-bit registers that hold 18 bits of RGB data for eachpixel. After the first row 110 is fully loaded, its enable signal 101goes high and its contents transfer to the second row 120. As a result,the columns 400 in row 110 can be loaded with data for future pixels.Upon completion of the loading, the data for an entire row of pixels isloaded into the second latch 120.

The SDC 100 always loads data into the latch 110 whether the deviceoperates in normal mode, three-bit mode or one-bit mode. Duringthree-bit mode, there are eight possible states for each sub-pixel:white, black, red, blue, green, and combinations of the colors toproduce yellow, cyan and magenta. In one-bit mode, the sub-pixels areall the same and each pixel is only white or black.

To save power in 3-bit mode the, the internal oscillator (not shown)will be divided by 4. This divided oscillator will clock all the digitalblocks. One or more unnecessary circuit blocks (e.g. backlight, notshown) are gated off to save power. Eight 3-bit pixels will be output ata time, and the address and address (bar) outputs will have the twoleast significant bits (lsbs) set to one, addressing eight, three-bitpixels at a time. The pix0 and pix1 outputs will pack the eight,three-bit pixels as shown in FIG. 4.

Pixel blocks always have 18 bits of data. For three-bit mode, the dataof pixels blocks pix0 and pix1 are loaded into the even/odd (left/right)columns as shown. The loading is redundant and repeated four times.However, after four loads, each latch will have at lest four bits foreach sub-pixel. The two least significant bits in each sub-pixel latchof the data bus are not used. In the one-bit mode, the data for allthree bits of one color are the same.

Source Driver Circuit: Decoders

Data for the row 120 is converted from digital to analog, one color at atime, in order to drive the source lines of the thin film transistors onthe display. The outputs of the row 120 are multiplexed to the columndecoders 60 by tri-sate buffers 50. At any one time a single color,six-bit word representative of red, or blue or green, is enabled andpassed to the decoder 60. In other words, the data in registers 13.1,13.2 and 13.3 in each latch are sequentially converted from digital toanalog voltages. Conversion is done simultaneously on each register 131(red) in each latch and repeated to convert first red, then blue andfinally green.

The decoders 60 convert digital signals to analog voltages. Each one isa 64-to-1 analog multiplexor. For a digital input from a register 13.1,13.2 or 13.3, the decoders 60 select one of sixty-four input analogvoltages. Those voltages drive the color pixel. Each decoder 60 iscoupled to the a 64-line output bus 250 of the Gamma Generator Circuit(GGC) 300. As will become clear below, each color in the GGC 300 has itsown gamma. Digital-to-analog conversion is performed serially, one colorat a time. For example, upon setting red select, the six-bit red wordfrom register 131 is input to the decoder 60. The decoder 60 receivessixty-four red reference voltage signals from which it selects thevoltage level that corresponds to the six-bit red word. The decoder 60is a 64-to-1 analog multiplexor in the form of a tree decoder. Suchdecoders are well known in the art. For any given six bit digital word,there is only one valid path through the decoder tree. The input end ofeach potential valid path is connected to one of the 64 referencevoltages and the digital signals from the register 13.1, 13.2 or 13.3set the valid path to connect the analog voltage that corresponds to thedigital signal.

There are level shifters 70 between the outputs of the tri-state buffers50 and the decoders 60. The level shifters is run in a digital domain tosave power. The digital voltage is about 1.8 volts and the analogvoltage is up to 5.5 volts. This feature helps conserve power becausepower is proportional to voltage squared. As such, as large a portion ofthe invention as possible operates in the digital domain as possible.

The analog output of the decoder 60 is connected to a 3-to-1 analogmultiplexor 61. It has three analog inputs including a first analoginput representative of six-bit data input for normal mode, and secondand third analog inputs representative of one-bit data inputs forone-bit and three-bit mode. It has two control signals. One selectsnormal mode for decoding the first analog signal and the other selectsthe second or third analog signal. During normal mode, the multiplexor61 receives the color (first) analog voltage and passes it to the pad 20of the display. However, during three-bit mode, multiplexor 61 takes thezero or one data from the second and third analog inputs and appliesthem to the pad 20.

The output of the multiplexor 61 is connected to amplifier 62 thatbuffers the analog voltage during 18-bit mode from the pad 20. Duringnormal mode, multiplexor 61 passes the decoded analog voltage output tothe operational amplifier 62. It buffers the color voltage signal andapplies it to the pad 20 of the column. However, during 3-bit operation,the operational amplifier 62 is powered down and a parallel switch inthe op amp 62 shunts the input to the output. As such, the output of themultiplexor 61 during three-bit mode is connected to the pad 20. Themultiplexor 61 receives a reference voltage directly from the GGC 300and applies the reference voltage directly to the pad 20 via the bypassconnection of the operational amplifier 62.

The LCD glass display has three thin film pass transistors, 40R, 40G, or40B, (one for each color) for each pixel. The channel driver hasseparate select signals Rs, Gs, and Bs for selecting the data for thered, green, or blue sub-pixel to be displayed. The glass panel has threeclock lines, CKH1 (red), CKH2 (green), and CKH3 (blue) that control,respectively, the operation of the red, green, and blue sub-pixels. Inone embodiment, the select signals Rs, Gs, and Bs and the clock signalsCKH1-3 may be the same or may be switched to be the same. In all cases,when CKH1 goes high, the red voltages for each of the columns areclocked into the red sub-pixels for the selected row. The colorselection and clocking is repeated for blue, green until the entire rowhas its color voltages. A timing controller (not shown) controls theclocking of the color select signals and the clock lines CKH1-3. Thetiming controller may be a separate block from the SDC or may be anintegral block within the SDC. Such configurations of timing controllersand channel driver circuits are known to those skilled in the art. Thetiming controller (not shown) moves from row to row until the display isfilled.

The thin film transistor 40R turns on when red is selected. The outputanalog voltage on the pad 20 is applied to the red sub-pixel in thefirst column of the display. All the red sub-pixels are enabledsimultaneously. The process is repeated for the other two colors untilthe row is entirely energized. The display is capacitive and thatfeature allows the sub-pixels to be rapidly set to their color leveldetermined by the six-bit color word. The capacitive feature holds thevoltage on the sub-pixels until the display is refreshed. As such, eachsub-pixel is energized rapidly to provide a mix of three colors and therows in the display are rapidly loaded to display a frame of an image.The sequencing of the illumination of the red, green, and bluesub-pixels occurs in too short a time to be notice by the human eye andthe capacitance of the display is sufficient to maintain the appearanceof continuous color.

Among the advantages of the invention is the common use of the decoders60, multiplexors 61, and operational amplifiers 62 by each color pixel.Instead of separate decoders and amplifiers for each color (3×320=960),the preferred embodiment has only one decoder and one operationalamplifier for all three colors.

Those skilled in the art understand that row select signals (not shown)are used to select the rows during each write to the display. The rowselect signals begin on the top or the bottom row and works row-by-rowuntil the entire display is written. Then the process begins again forthe next frame of video. The number of rows is arbitrary. In thepreferred embodiment, there are 480 rows. However, those skilled in theart understand that a display may have more or fewer rows and the SDC isconfigured to drive all the rows in the selected display.

Source Driver Circuit: Gamma Generator Circuit (GGC)

The GGC block 300 is shown in FIG. 15. It is a network of eighty rangeresistors 390, five range decoders 370, five range amplifiers 350, areference resistor string 330 with sixty-four reference voltage outputs310.00-310.63 and sixty-four, 4-to-1 analog multiplexors 320. Forheuristic purposes, FIG. 15 shows only five output multiplexors. Theoutputs of the 64 multiplexors 320 are placed on the 64 bit output bus250 to provide a selection of 64 reference voltages to the DACs 60 ofthe output channels. The GGC is capable of generating separate gammavalues for each color, both for positive and negative voltages. The GGCovercomes the problem of look up tables and instead is a real timeanalog voltage generator for the LCD display. The GGC is also capable ofswitching on the fly from one gamma curve to another to enable thedisplay to have different gammas for each color. The GGC is adjustableto be compatible with gammas for different displays. Each gamma valuemay be altered to accommodate different displays.

Those skilled in the art understand that the polarity applied to theliquid crystals should be reversed periodically. If a single polarityvoltage is continuously applied to a liquid crystal the crystal maybecome permanently oriented or lose its ability to change. As a result aghost image will be imposed on the display. In order to avoid thisproblem the voltages 301, 302 on the gamma reference network areperiodically reversed to provide opposite polarity voltages to thelines/rows of the display. A typical technique is line inversion whereeach line has a first polarity voltage applied in one frame and anopposite polarity voltage applied in the next frame. Another techniqueis pixel inversion where adjacent pixels a first frame have oppositepolarities and the polarities on the pixels are reversed on the nextframe.

Inversion is accomplished by the reversal of the polarity signal in FIG.15A. This in effect “flips” the range resistor string by applying a lowvoltage to the upper end and a high voltage to the lower end or viceversa. Once these voltages are changed, the voltages propagate throughthe gamma reference and the gamma curve is inverted without anyadditional circuit changes.

The operation of the GGC 300 is best explained from the referenceresistor string 330 back to the input range resistor string 390. The GGCoutputs sixty-four reference voltages ranging from zero (VREFMIN) to amaximum (VREFMAX). However, the sixty-four outputs are not linear. Thoseskilled in the art understand that the driving voltages for and LCDshould vary non-linearly. Human perception of color is not linear andthus the reproduction of color images by LCDs must be nonlinear in orderto appear acceptable to the viewer. In addition the transmissivityresponse of the LCD is non-linear and it too must be built into thegamma curve.

In the preferred embodiment, the decoders 60 have sixty-four referencevoltages. Those reference voltages are found at taps 310.00-310.63 onthe reference resistor string 330. The non-linearity is programmed intothe reference resistor string 330 in several ways. First, the spacingbetween the taps is not equal. As such, voltage drops between sequentialtaps are different. Second, the reference voltages at five taps (0, 7,24, 56, and 63) on the string 330 are driven by five operationalamplifiers 350. Those amplifiers are connected to range DACs 370 thatselect the reference voltage from the range resistor string 390. Thisprovides a coarse adjust of the gamma curve and allows the user to havedifferent gamma curves on the fly for red, green, or blue, positive andnegative. In effect, this is six sets of voltages.

The input range resistor string 390 has 80 taps that are equally spacedfrom each other. The string 390 provides a linear voltage divider ofequal voltage divisions. There are five range DACs 370. Each range DACselects one of 32 possible reference voltages available on the rangeresistor string 390. For example, DAC 371 may connect to any tap between0 and 32; DAC 372 may connect to any tap in the range 12-44; DAC 373connects to taps 24-56; DAC 374 connects to taps 36-68 and DAC 375connects to taps 48-80. Range DACs 370 allow the user to modify thegamma output voltages of the output reference resistor string 330 bymodifying the input voltages to resistor string 330. For example, thereference voltage at location 24 on the reference resistor string 330can be adjusted by altering the tap input to range DAC 373. Of course,that will affect the voltages between locations 7 and 56. Voltages areonly driven at five locations, 0, 7, 24, 56 and 63. Voltages betweenlocations are determined by the selected location between two drivenlocations. For example, the voltages between locations 24 and 7 are theresult of a voltage divider that has non-uniform steps between locations24 and 7. In order to achieve this result, the outputs of 4-to-1multiplexors 322 at locations 7, 323 at location 24 and 325 at location56 are connected to the outputs of their respective range amplifiers,352, 353 and 354.

The voltage drop across the range resistor string 330 varies from thehigh reference voltage V_(HR), typically 3-5 volts, to the low referencevoltage V_(LR), typically ground, or zero. Although there are only 80resistances, each DAC 370 receives thirty-two reference voltages fromthe range resistor string 390. As such, there is a relative largeoverlap of reference voltages among the DACs 370. The outputs of theDACs 370 are the break points of a four-segment non-linear curve. Thosesegments correspond to the four adjustable regions: 63-56, 56-24, 24-7and 7-0. Each range DAC is individually selectable to establish areference voltage at one of the ends of the range. DAC 375 sets voltageat level 63, DAC 374 set the voltage at level 56, DAC 373 sets thevoltage at level 24, DAC 372 set the voltage at level 7 and DAC 371 setthe voltage at level 0. The voltage drop from one region to the next isdifferent and the individual steps are nonlinear.

For example, FIG. 5 displays a typical gamma curve for one color. It has64 nominal levels. Between level 63 and level 56, the output voltage mayvary by one volt. However, between level 56 and level 24, the voltagechange is about 0.4 volts. Between the level 24 and level 7, the voltagechanges by about 0.7 volts. Between level 7 and level 0, the change isalmost two volts. Stated another way, the resistance value between tap63 and 62 is not the same at the resistance value between the tap 62 and61. Tapping into the reference resistor string at different and unequallocations generates the nonlinear gamma output.

The GGC of the preferred embodiment divides the gamma curve into fouradjustable curve regions: 63-56, 56-24, 24-7 and 7-0. The range DACdetermines one end of each region and the output taps determine theother end of the curve region. The maximum output voltage, approximately4 volts, is at level 63 and the minimum voltage, zero, is at level 0.The voltages at levels 63, 56, 24, 7 and 0 may be configured to thedisplay specifications.

Source Driver Circuit: Low Power Mode

The low power mode may use one bit or three bits. In the one bit mode,users often prefer to use black and white. However, it is also possibleto use any color that can be created using the range of voltages thatcan be supplied by the DACs 375 & 371 in FIG. 15A. One color may be abackground color and the other color a foreground color. It is alsopossible to switch from one foreground color to another. For example,when battery power is low, a manufacturer could set the gamma generatorcircuit to switch the foreground color from white to red and thus usethe color to warn of low power in addition to a text message or lowpower image. In three bit mode, the sub-pixels switch differently toprovide color. In the one bit mode the sub-pixels switch the same (i.e.,have the same value) to provide only two colors, typically black andwhite.

In typical low power mode the colors are at their maximum values and onemay generate red, green, blue, cyan, magenta, yellow, black and white.Three bit mode uses primary colors (red, green, or blue) or combinationsof those colors. Each color may be high or low. However, a feature ofthe invention is that the colors may be set to less than their maximumor minimum. As such, a lighter shade of red (a voltage less than thehighest possible voltage) is selectable. Selection is made by the rangemultiplexors 320, 321. By setting red at less than its maximum value andother colors at their maximum, the red contribution is reduced. In thisway, by varying the contribution from each color, the gamma circuit isnot limited to the basic combinations of red, green and blue, but rathera set of eight (in 3-bit mode) or two (in 1-bit mode) custom colors.

One of the features of the invention is its flexibility to provideoptimum power in normal mode and to save power in low power mode. Innormal mode, each channel (column) is individually driven by a bufferamplifier 62. However, in low power mode, the buffers 62 are shut downand the display is centrally driven by only two of the range amplifiers.During low power mode, operational amplifiers 62 in the output channelsand range amplifiers 353-355 in the GGC 300 are powered down and all thegamma multiplexors 320 are disconnected. A bia circuit boosts the powerto range amplifiers 351 and 352 by enough to drive the display from acentral gamma reference.

In low power mode, the channel driver needs only a high and low voltage.Since only the high and low voltages are used, the reference resistorstring 330 is not needed and it is effectively disconnected to savepower. The low power voltages are not decoded. Instead, the analogvoltage corresponding to the low power mode signal is directly connectedto the multiplexors 61 in the output channels. As such, the bias blockand the two range amplifiers 351, 352 power the display. A color modemultiplexor 340 is coupled to the high reference voltage 63 and to theoutput of the DAC 372. When color mode is selected and the device enterslow power mode, the high reference voltage at location 63 is connecteddirectly to the second range amplifier 352. Only two valid referencevoltages appear and they are at locations 0 and 7 and are applied to thebus 250. Compared to other circuit traces, the circuit traces that carryvoltage and current from the zero and 7 locations to the channelmultiplexors 61 are larger than the rest. The larger size reduces theresistance which in turn enables the display to be driven from a centrallocation.

In low power three-bit mode, the channel driver performs data packing asexplained above in connection with FIG. 16. Referring to FIG. 14, thetri-state switches 50 receive the three-bit data. Each color is, ineffect, demultiplexed and passed to the multiplexor 61 via the LSBs thatcontrol the multiplexer via the dotted line connection 51. The gammamultiplexors 320 are powered down and this eliminates the possibility ofcontention during three-bit mode.

Source Driver Circuit: Manufacturer Adjustments

The 64 gamma multiplexors 320 allow the manufacturer to adjust theindividual tap points of the reference resistor string 330. Eachmultiplexor has four or more input tap points. A select signal on themultiplexor allows the user to select desired tap points. The reasonthere are not 64 DACs, one for each gamma reference voltage, is thatreference voltages 0 and 63 are always endpoints of the curve and arealways connected to the ends of the reference resistor string.

The 64 gamma output multiplexors 320 permit further adjustment. Forexample, in the preferred embodiment each gamma multiplexor 320 is a4-to-1 analog multiplexor for generating four distinct gamma curves.However, the multiplexors could be of any size, greater or smaller thanthe preferred embodiment, including, and not limited to, for example,8-to-1 or 3-to 1.

A gamma generator circuit 300B with an alternate low power color palateis shown in FIG. 15B. The GGC 300B has two 64-to-1 DACs 376, 377connected to the range resistor string 390. Color registers in block 394set the DACs 376, 337 to select one of the locations on the referenceresistor string 390. Each DAC 376, 377 may select one of 80 voltagesfrom the full range of the range resistor string 390. One of the DACs isset for a higher voltage and one for lower. The color register settingslets the manufacturer individually adjust the on and off intensity ofeach of the colors red, blue, green, to provide more colors for lowpower mode. In operation, control signals in the multiplexors 340, 341select the outputs of the DACs 376, 377 and other controls shut downDACs 371-375, and range amps 353, 354, 355. Range amplifiers 351, 352have their inputs connected to the outputs of the select multiplexors340, 341. The amplifier outputs are connected to lines 252, 253 fordirectly driving the display. As explained above, the lines 252, 253 arethe larger trace lines of the gamma output bus 250. Thus, only twooutput lines are driven in low power mode.

An alternate method provides more color resolution by adding a 64-to-1multiplexor at the output of the reference resistor string 330 and keepthe range amplifiers 350 powered up during three-bit mode. That wouldprovide 64 output reference voltages, which could be applied directly tothe pads 20. For example, one skilled in the art could leave all thegamma multiplexors powered up, use the multiplexors to select the highand low voltage for the a given color, and then directly apply the colorfrom the gamma multiplexors to the channel drivers. One would need twoadditional 64-to-1 multiplexors and two buffers to drive the columnsdirectly from the gamma reference block. This would allow a user toselect a color in low power mode in a manner similar to the ability innormal mode. In effect, one could have one independent color and sevenother colors dependent on the one independent color.

Gamma generator circuit 300C diagrams this approach and is shown in FIG.15C. There 64-to-1 decoders 378, 379 are connected to the 64 bit outputbus 250. Inputs to amplifiers 358, 359 are connected, respectively, tothe outputs of the decoders 378, 379 and the amplifier outputs areconnected to larger-than-normal output lines in bus 250 to drive thedisplay. Color registers 391, 392 set the color levels in the decoders378, 379. In operation, the entire gamma circuit 300C remains fully on.While this embodiment consumes more power, it has the added advantage ofa broader selection of colors because the color selection is made fromthe 64 bit output of the GGC 300C.

In the embodiment of FIG. 15B the decoders 376, 377 each have 32 tapsfor handling five bits. However, they could handle six bits if they had64 taps. The registers 394 select the high and low setting for each ofthe red, green and blue colors.

In the GGC 300C, DACs 378, 379 have a full range of color available toit in contrast to the limited range available in GGC 300A. Likewise, inGGC 300C, its decoders 378, 379 also have a full range of color.

Referring to FIG. 18, in accordance with an embodiment of the presentlyclaimed invention, a commercial product of the assignee, NationalSemiconductor Corporation, includes a command and configuration stage, alow-speed serial interface (LoSSI), a partial display memory, a videointerface, a MPL receiver, an EEPROM, a timing controller, levelshifters, an oscillator, a DC-DC converter, a source driver, a gammareference and a V_(COM) driver, interconnected substantially as shown.

The Command and Configuration block contains the Command Interpreter andConfiguration Registers which control the functions, settings, andoperating modes of the device. There are two methods that may be used tocontrol the device and modify the Configuration Registers. In CommandMode, OpCodes received from the LoSSI Interface cause mode changes orchanges to the Configuration Registers based on the OpCode received andthe “command profile” stored in the EEPROM. Device control using theCommand Mode is beneficial in that it allows the host processor displaydriver software to be display independent. In Register Access Mode, theLoSSI Interface directly accesses the Configuration Registers. Uponassertion of hardware reset (RESET_N pin), the device is placed in theCommand Mode. Register Access Mode can be selected from the LoSSIinterface by issuing the Enter Register Access Mode command. CommandMode can be selected from the LoSSI interface by issuing the EnterCommand Mode OpCode.

The LoSSI interface is used for several functions: send commands; accessthe Configuration Registers; and send data to the Partial DisplayMemory. The LoSSI interface uses either the SPI or TSI protocol asdetermined by the state of the SPI_CFG pin. The LoSSI interface signalsuse CMOS logic levels (GND, V_(DDD)). The LoSSI interface includes foursignals: SP_CSX (chip select input) is low-active; SP_CLK (serial clockinput) is the data transfer synchronization signal, may operate atspeeds up to 10 MHz during register writes or command operations, or upto 6.6 MHz during register read operations, and should be set high whenidle; SP_DI (serial data input) is the serial data input pin and issampled at the rising edge of SP_CLK; and SP_DO (serial data output) isthe serial data output pin and is held in a high-impedance state exceptwhen data is being driven out during read operations. The SP_DI andSP_DO signals may be tied together if the host processor supportsbi-directional data transfer. Two protocols are supported across theLoSSI interface: an 8-bit protocol (SPI protocol) and a 9-bit protocol(TSI protocol) which includes an extra bit at the beginning of eachtransaction. The SPI protocol is selected by connecting the SPI_CFG pinto VDD.

The extra bit in the TSI protocol (Data/Command or D/CX) is useful inCommand Mode to identify the subsequent 8-bits as either a command ordata field. This can be helpful to recover from a partially completedcommand argument transfer. For example, this condition might occur if ahost interrupt occurs while transferring image data to the PartialDisplay Memory. If the TSI protocol is utilized, it is possible toterminate an in-process transaction and abort the transfer of theremaining data. Then after processing the interrupt, the remaining datacan be sent to the Partial Display Memory without re-issuing the commandand previously sent data by identifying the transaction as a datatransfer as opposed to a command. Alternatively, if the SPI protocol isused, it is still possible to service an interrupt and suspend datatransfer as long as the LoSSI chip-select (SP_CSX) and clock signal(SP_CLK) are held in their current state until data transfer can resume.

The Partial Display Memory block is used to store image data for localrefresh of the display. It can be used as the sole video source inPartial Mode or its contents can be blended with (or overlaid on) theincoming video data in Alpha Mode. While operating in Partial Mode,system power is greatly reduced because the video controller in thesystem may be shut down. In this mode, image data is read from thePartial Display Memory and used to refresh the display. All displayrefresh timing is derived from an internal oscillator, thus no externalvideo signals are required. In Alpha Mode, the Partial Display Memorycontents can be used as a transparent text or border overlay on theincoming video data. It is also possible to blend the contents of thePartial Display Memory to add full-color logos and other effects to thevideo data. The Partial Display Memory contains 230,400 bits of memory.This size is sufficient to display an 80×320 window of 3-bit data, orany equivalent size in terms of the total pixels contained in thePartial Display Window multiplied by the color depth of each pixel. InRegister Access Mode, image data should be streamed in raster-order intothe Partial Display Memory by writing data to the RAM_PORT register asdescribed in the next sections. In Command Mode, the Memory Writecommand is used to send image data to the Partial Display Memory.

During Partial Mode, pixel data is read from the Partial Display Memoryand displayed in a rectangular Partial Display Window as shown in FIG.11. Regions outside this window are blanked to minimize power. The colorof the blanked regions is specified in the Partial Mode Border Colorregisters. The raster always begins at the starting row and startingcolumn. The column is incremented first thus, the raster is filled fromleft to right and then from top to bottom.

Supported color depths for the Partial Display Window include 1-bit,3-bit, 12-bit and 18-bit. In Command Mode, the color depth is set viathe PM Color Set command (EEh OpCode). In Register Access Mode, thePartial Display Window color depth is controlled by the BITS_PER_PIXELregister. The maximum size of the Partial Display Window is related tothe number of bits in the Partial Display Memory and to the color depthsetting. The Partial Display Memory can fill a complete 320×560 screenfor 1-bit color depth operation, 76,800 3-bit pixels (e.g. 240×320×3-bitwindow), 19,200 12-bit pixels (120×160×12-bit window) and 12,800 pixelsin 18-bit color depth operation (128×100×18-bit window). The window sizefor the partial display window can be doubled in both dimensions throughthe use of an upscale feature. In order to maximize the useable memoryfor each color depth, the image data is packed into the Partial DisplayMemory based on the color depth setting. It is then unpacked to thecurrent color depth setting as it is read out for Partial Displayrefresh. Therefore, if the size or color depth of the Partial DisplayWindow is changed, the Partial Display Memory is reloaded with updatedimage data corresponding to the new window settings. There is also arelationship between the Partial Mode color depth setting and the pixeldata packing on the LoSSI interface as is illustrated in FIG. 5.

A pixel scaling function enables incoming video or image data stored inthe Partial Display Memory to be up-scaled by a factor of 2 in both thex-dimension and y-dimension. In this manner, a single pixel is mappedinto a 2×2 cluster of pixels.

The number of pixels sent correspond to a whole number of bytes.Accordingly, dummy pixels may be sent, so long as the total number ofpixels sent does not exceed the capacity of the memory. Preferably, thePartial Display Memory word size is fixed. To efficiently use theavailable bits in the Partial Display Memory, the pixel data is packedinto the fixed memory word size. Incoming pixel data is not written intothe memory until all the bits of the memory word have been filled.Therefore, it may be necessary to pad extra bits onto the end of thedata stream so that the data stream contains an integral multiple of 36bits.

The Timing Controller block generates the timing signals required toload data into the source driver and controls the scanning of thedisplay. The display may be operated in one of three modes: Normal Mode,Partial Mode or Alpha Mode. In Normal Mode, the display scan timing isdeveloped from the DE and PCLK signals and the video data stream. Thedata displayed is obtained from the video data stream. In Partial Mode,the display is self-refreshed by the Timing Controller block using theon-chip Oscillator block as the clock source. The data sent to thedisplay is read from the internal Partial Display Memory. In Alpha Mode,the display scan timing is also developed from the DE and PCLK signals,and data obtained from the video stream is displayed in the background.In addition, data is read from the internal Partial Display Memory anddisplayed in a partial display window in the foreground. Within thiswindow, the foreground and background may be blended in one of fourratios: 25% foreground+75% background; 50% foreground+50% background;100% foreground; or Transparent foreground (OSD function).

The Timing Controller block is designed to interface with manyconfigurations of LTPS/CGS glass: single-phase or two-phase verticalclocking; RGB or BGR subpixel ordering for horizontal scanning; timingpulse widths and non-overlap times which are register-adjustable tooptimize display settling performance; polarity and phasing of glasssignals controlled via register settings; and vertical timingrelationships associated with various configurations of dummy lines onthe glass controlled by register settings.

The Timing Controller block has ten outputs that are designed to controlthe display refresh and scanning. The Level Shifter block performs logiclevel translation for these signals such that they can interfaceproperly to the glass control inputs. The output voltage for the levelshifter signals is V_(SSG) to V_(DDG). There are 3 outputs (GPO_0,GPO_1, GPO_2) whose signal function changes depending on the setting ofthe GPO register. All level shifter outputs are driven to GND when inthe Sleep state.

An additional level-shifted output XDON is provided by the DC-DCconverter block. Normally, XDON is at the V_(SSG) level wheneverV_(DDDC) is present. If V_(DDDC) is suddenly interrupted, XDONimmediately goes to the V_(DDG) level. Because there is externalcapacitance on the V_(DDG) and V_(SSG) nodes, XDON will persist at theV_(DDG) level for a brief period of time after V_(DDDC) is interrupted.Thus, XDON may be reliably used by the glass as a control signal todischarge all nodes on the glass in the event of a sudden powerinterruption.

The on-chip oscillator generates a 13.5 MHz internal clock signal (OSC).The OSC signal is used as the clock source for the Timing Controllerblock during Partial Mode and during certain command sequences such asthe power-down sequence.

The Source Driver block converts the digital image data received fromthe MPL interface or Partial Display Memory to analog voltages requiredto drive the source lines on the glass. The source driver block consistsof 320 drive channels. Each drive channel receives RGB data for onepixel and performs a D/A conversion of the red, green and blue data in atime-multiplexed sequence that is synchronized to the glass multiplexselect signals (CKH1-3). The conversion sequence of the RGB data withineach line time is determined by the SCAN register settings. The SCAN[1]register bit controls the data loading direction of the Source Driverblock, S0→S319 or S319→S0 direction. For display applications in whichthe pixels/line on the glass is less than 320 channels, the COL_OFFSETregister can be used to specify which outputs are active and whichoutputs are unused by the application. This can help optimize the sourceline fan-out region between the driver and the glass active region. TheCOL_OFFSET is specified in conjunction with the SCAN[1] setting. If theload direction is set for the S0→S319 direction, then the COL_OFFSET isreferenced to the S0 output. If the load direction is set for theS319→S0 direction, then the COL_OFFSET is referenced with respect to theS319 output. The voltage transfer characteristic of the source driverDAC is determined by the 64 gamma reference voltages generated by theGamma Reference block. The drive strength for the source driver outputis also programmable to optimum settling and power performance via theGAMMA_CFG1[4:0] register bits.

Four intrinsic gamma curves are available for the 64 reference voltages.The intrinsic curves can be used to accomplish various goals for themodule user. One goal might be to obtain matching optical performancefrom various module suppliers. It is even possible to optimize theindividual curve shapes for the different color channels of a givensupplier. In these cases, the four curve options can be optimized foreach of the module supplier's glass characteristics and the selection ofthe proper curve and settings is included in the SLEEP_OUT command. TheGAMMA_SET command is not used in this case as the other choices areoptimized for a different module supplier. Another reason for usingmultiple intrinsic curve settings might be to provide multiple gammacharacteristics (e.g. γ=1.0, 1.8, 2.2, 2.5) for a given module in orderto optimize performance for various viewing conditions and applications.In this case, the various curves can be selected via the Gamma Setcommand or through direct register access to Gamma Register settings.

Referring to FIGS. 19A and 19B, which illustrate possible negative andpositive intrinsic curve shapes, respectively, after selecting theintrinsic curve which most closely matches the desired characteristic,the curve shape can then be optimized to better match the desiredcharacteristic through the use of the gamma register settings. The shapeand gamma labels in these figures are for illustration purposes only.The GAMMA_CFG1[7] register bit determines whether one of these fourshapes is used with all three color channels or if separate curves oradjustment settings are selected for each color channel. This sameintrinsic shape may be used for the green and blue curves with differentoptimization settings (see below discussion of optimization settings),or different intrinsic shapes and optimization settings may be chosenfor each color channel. For a given color channel, the same intrinsiccurve shape will be used for both drive polarities.

Referring to FIG. 20, values can be generated in accordance withequations for four intrinsic gamma curves as shown. Referring to FIG.21, the selected intrinsic curve shape may be optimized by setting thevoltage values of the endpoints (V0 and V63) and of three taps (V7, V24and V56) via range adjustment DACs (referred to as Range DACs).According to an example embodiment, the settings for the positivepolarity gamma curve are independent from those for the negativepolarity gamma curve, though the same intrinsic curve shape will be usedfor both drive polarities. The voltages for V0, V7, V24, V56 and V63 aredetermined by the V_(GR) reference voltage which is adjustable to matchthe curve dynamic range by the VDD_ADJ[7:5] register bits and the GammaReference registers. The settings for VDDA and VGR in the VDD_ADJregister should be determined as follows: calculate VGR setting requiredbase upon the most positive value of VcomH, VcomA, V0+ or V63− usingpredetermined relationships; and calculate the value of VDDA from themaximum value for VGR, VDDGR, VSSGR plus operating voltage headroom.

Referring to FIG. 22, the architecture of the Gamma Reference block canbe implemented as shown (for simplicity, only the Range DAC optimizationregisters for the red channel are shown). The DRIVE POLARITY signal isprovided by the Timing Controller and does two things: select theadjustment values for either the negative or for the positive drivepolarities, for each of the colors (green and blue registers are notshown); and select the correct output voltage ranges for the D/Aconverters. For negative drive polarity, the D/A for V₀ will generate avoltage near ground, and the D/A for V₆₃ will generate a voltage nearV_(GR) (FIG. 19A). For positive drive polarity, the D/A for V₀ willgenerate a voltage near V_(GR), and the D/A for V₆₃ will generate avoltage near ground (FIG. 19B). If GAMMA_CFG1[7]=0, the RGB selectsignals will always select the values corresponding to the red channel.If GAMMA_CFG1[7]=1, the RGB select signals from the Timing Controllerselect the red, green or blue gamma values according to the CKH1, CKH2and CKH3 clocks and the RGB/BGR select bits (SCAN[7] and SCAN[0]).

Referring to FIG. 23, DC V_(COM) or AC V_(COM) drive may be selected bythe VCOM_ADJ[7] register bit. The AC VCOM drive scheme utilizes twodevice pins and an external coupling capacitor. In this mode, theVCOMA_VCS pin (Pad 1) is functioning to output the VCOMA signal to thecoupling capacitor. The second device pin, VCOMH_VCOM (Pad 2), isfunctioning to establish the dc value of the V_(COM) node during thehigh time of the waveform. The AC V_(COM) Mode is selected by settingVCOM_ADJ[7]=1. The V_(COM) AC signal is provided at the VCOMA_VCS pads.The amplitude of this signal is set by the VCS_ADJ register.

The VCOMH_VCOM output is used to clamp the V_(COM) high level, andshould be connected directly to the V_(COM) line to the glass. IfVCOM_ADJ[6]=0, this high level is determined by VCOM_ADJ[5:0]. IfVCOM_ADJ[6]=1, this high level is adjusted by an external voltageconnected to the VCOM_ADJ pin. The VCOMH_VCOM pads should be connecteddirectly to the V_(COM) input of the glass, and the VCOMA_VCS padsshould be connected through a large capacitor to the V_(COM) input tothe glass.

During time t₁, pad 1 (VCOMA_VCS signal) is driven to the voltageV_(COMA) and pad 2 (VCOMH_VCOM signal) is driven to the voltageV_(COMH). As a result, the V_(COM) voltage to the glass will be equal toV_(COMH) and the external capacitor will be charged to a voltage of(V_(COMH)-V_(COMA)). During time t₂, pad 1 is driven to ground and pad 2is floating. Because the external capacitor remains charged to a voltageof (V_(COMH)-V_(COMA)), the voltage on pad 2 (the V_(COM) signal to theglass) will be also equal to (V_(COMH)-V_(COMA)). Thus, the V_(COM)voltage applied to the glass will swing between V_(COMH) and(V_(COMH)-V_(COMA)).

The DC V_(COM) Mode is selected by setting VCOM_ADJ[7]=0. In this casethe DC V_(COM) voltage to the glass is provided by the VCOMH_VCOMoutput. The C_(STORE) voltage to the glass (VCS) is provided by theVCOMA_VCS output. The DC level of VCOMA_VCS is set by the VCS_ADJregister.

Flicker is minimized by setting the VCOMH_VCOM level either by changingthe VCOM_ADJ[5:0] register or by adjusting an external voltage connectedto the VCOM_ADJ pin. If the register method is used, then the optimizedvalue for the VCOM_ADJ register should be included in the Sleep Outinitialization profile in the EEPROM such that the register is alwaysset to the optimized value during the power-up sequence. Alternatively,if multiple gamma curves and Vcom settings are used in the operation ofthe device, the optimized VCOM_ADJ setting can be included in theappropriate Gamma Set command profile. In this manner, it is possible tooptimize flicker independently for each Gamma Curve selection.

While the invention has been described with reference to particularembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings of the invention without departing from thescope of the invention.

Therefore, it is intended that the invention not be limited to theparticular embodiments disclosed as the best mode contemplated forcarrying out this invention, but that the invention will include allembodiments falling within the scope and spirit of the appended claims.

1. A method for using a data enable signal and pixel clock exclusive oftheir associated horizontal and vertical synchronization signals for adigital video signal to facilitate generating of signals correspondingto said associated horizontal and vertical synchronization signals,comprising: receiving a pixel clock having a plurality of periodic clockpulses; receiving a data enable signal with asserted and de-assertedstates separated by leading and trailing signal edges; counting firstand second portions of said plurality of pixel clock pulsescorresponding to time intervals between unlike ones and like ones ofsaid leading and trailing signal edges to produce at least first andsecond pixel clock counts, respectively; comparing respective ones ofsaid plurality of first pixel clock counts to produce a first comparisoncount with a first learned value indicative of a difference betweenfirst and second ones of said plurality of first pixel clock counts;comparing respective ones of said plurality of second pixel clock countsto produce a second comparison count with a second learned valueindicative of a difference between first and second ones of saidplurality of second pixel clock counts; and counting each one of aplurality of successive portions of said plurality of pixel clock pulsesthrough a count equal to said second learned value in a succession ofpixel counts to produce a pixel count signal indicative of a horizontalline interval, and a total line signal indicative of a vertical lineinterval.
 2. The method of claim 1, wherein said counting first andsecond portions of said plurality of pixel clock pulses corresponding totime intervals between unlike ones and like ones of said leading andtrailing signal edges to produce at least first and second pixel clockcounts, respectively, comprises: counting a plurality of portions ofsaid plurality of pixel clock pulses corresponding to respective timeintervals between successive unlike ones of said leading and trailingsignal edges to produce a plurality of first pixel clock counts; andcounting a plurality of portions of said plurality of pixel clock pulsescorresponding to respective time intervals between successive like onesof said leading and trailing signal edges to produce a plurality ofsecond pixel clock counts.
 3. The method of claim 2, wherein saidcounting a plurality of portions of said plurality of pixel clock pulsescorresponding to respective time intervals between successive unlikeones of said leading and trailing signal edges to produce a plurality offirst pixel clock counts comprises counting a plurality of portions ofsaid plurality of pixel clock pulses corresponding to a plurality of oneof said asserted and de-asserted states of said data enable signal. 4.The method of claim 2, wherein said counting a plurality of portions ofsaid plurality of pixel clock pulses corresponding to respective timeintervals between successive like ones of said leading and trailingsignal edges to produce a plurality of second pixel clock countscomprises counting a plurality of portions of said plurality of pixelclock pulses corresponding to successive ones of said asserted andde-asserted states of said data enable signal.
 5. The method of claim 1,wherein: said comparing respective ones of said plurality of first pixelclock counts to produce a first comparison count with a first learnedvalue related to a difference between first and second ones of saidplurality of first pixel clock counts comprises comparing first andsecond successive ones of said plurality of first pixel clock counts toproduce a first comparison count, wherein said first comparison counthas a value which changes from a first prior value and to a firstlearned value corresponding to said second one of said plurality offirst pixel clock counts when said first and second ones of saidplurality of first pixel clock counts are equal; and said comparingrespective ones of said plurality of second pixel clock counts toproduce a second comparison count with a second learned value related toa difference between first and second ones of said plurality of secondpixel clock counts comprises comparing first and second successive onesof said plurality of second pixel clock counts to produce a secondcomparison count, wherein said second comparison count has a value whichchanges from a second prior value and to a second learned valuecorresponding to said second one of said plurality of second pixel clockcounts when said first and second ones of said plurality of second pixelclock counts are equal.
 6. The method of claim 5, wherein said comparingfirst and second ones of said plurality of first pixel clock counts toproduce a first comparison count comprises comparing successive ones ofsaid plurality of first pixel clock counts.
 7. The method of claim 5,wherein said comparing first and second ones of said plurality of secondpixel clock counts to produce a second comparison count comprisescomparing successive ones of said plurality of second pixel clockcounts.
 8. The method of claim 1, wherein said counting each one of aplurality of successive portions of said plurality of pixel clock pulsesthrough a count equal to said second learned value in a succession ofpixel counts to produce a pixel count signal indicative of a horizontalline interval, and a total line signal indicative of a vertical lineinterval further includes producing: a vertical count signal indicativeof a first portion of said succession of pixel counts during which saiddata enable signal includes one of said asserted and de-asserted states,and a second portion of said succession of pixel counts during whichsaid data enable signal includes both of said asserted and de-assertedstates; and an active line signal indicative of said second portion ofsaid succession of pixel counts.